package org.jikesrvm.compilers.opt.ia32;
import org.jikesrvm.*;
import org.jikesrvm.compilers.opt.*;
import org.jikesrvm.compilers.opt.ir.*;
/**
* This class is the automatically-generated assembler for
* the optimizing compiler. It consists of methods that
* understand the possible operand combinations of each
* instruction type, and how to translate those operands to
* calls to the VM_Assember low-level emit method
*
* It is generated by GenerateAssembler.java
*
*/
public abstract class OPT_Assembler extends OPT_AssemblerBase {
/**
* @see VM_Assembler
*/
public OPT_Assembler(int bcSize, boolean print, OPT_IR ir) {
super(bcSize, print, ir);
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a DIVSS operator
*
* @param inst the instruction to assemble
*/
private void doDIVSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitDIVSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_CompareExchange8B instruction
* and has a CMPXCHG8B operator
*
* @param inst the instruction to assemble
*/
private void doCMPXCHG8B(OPT_Instruction inst) {
if (isRegDisp(MIR_CompareExchange8B.getMemAddr(inst))) {
emitCMPXCHG8B_RegDisp(
getBase(MIR_CompareExchange8B.getMemAddr(inst)), getDisp(MIR_CompareExchange8B.getMemAddr(inst)));
} else {
if (isRegOff(MIR_CompareExchange8B.getMemAddr(inst))) {
emitCMPXCHG8B_RegOff(
getIndex(MIR_CompareExchange8B.getMemAddr(inst)), getScale(MIR_CompareExchange8B.getMemAddr(inst)), getDisp(MIR_CompareExchange8B.getMemAddr(inst)));
} else {
if (isRegIdx(MIR_CompareExchange8B.getMemAddr(inst))) {
emitCMPXCHG8B_RegIdx(
getBase(MIR_CompareExchange8B.getMemAddr(inst)), getIndex(MIR_CompareExchange8B.getMemAddr(inst)), getScale(MIR_CompareExchange8B.getMemAddr(inst)), getDisp(MIR_CompareExchange8B.getMemAddr(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_CompareExchange8B.getMemAddr(inst))) VM._assert(false, inst.toString());
emitCMPXCHG8B_RegInd(
getBase(MIR_CompareExchange8B.getMemAddr(inst)));
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a SUBSD operator
*
* @param inst the instruction to assemble
*/
private void doSUBSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUBSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FDIVP operator
*
* @param inst the instruction to assemble
*/
private void doFDIVP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFDIVP_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPEQSS operator
*
* @param inst the instruction to assemble
*/
private void doCMPEQSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPEQSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Compare instruction
* and has a FCOMIP operator
*
* @param inst the instruction to assemble
*/
private void doFCOMIP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitFCOMIP_Reg_Reg(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Compare instruction
* and has a UCOMISD operator
*
* @param inst the instruction to assemble
*/
private void doUCOMISD(OPT_Instruction inst) {
if (isReg(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISD_Reg_Reg(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isAbs(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISD_Reg_Abs(
getReg(MIR_Compare.getVal1(inst)),
getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISD_Reg_RegDisp(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISD_Reg_RegOff(
getReg(MIR_Compare.getVal1(inst)),
getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISD_Reg_RegIdx(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitUCOMISD_Reg_RegInd(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a CVTTSD2SI operator
*
* @param inst the instruction to assemble
*/
private void doCVTTSD2SI(OPT_Instruction inst) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSD2SI_Reg_Reg(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSD2SI_Reg_Abs(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSD2SI_Reg_RegDisp(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSD2SI_Reg_RegOff(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSD2SI_Reg_RegIdx(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitCVTTSD2SI_Reg_RegInd(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Compare instruction
* and has a FCOMI operator
*
* @param inst the instruction to assemble
*/
private void doFCOMI(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitFCOMI_Reg_Reg(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a SHR operator
*
* @param inst the instruction to assemble
*/
private void doSHR(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSHR_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSHR_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSHR_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitSHR_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSHR_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSHR_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitSHR_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSHR_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSHR_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSHR_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHR_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHR_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHR_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHR_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHR_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHR_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHR_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPNESD operator
*
* @param inst the instruction to assemble
*/
private void doCMPNESD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPNESD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a AND operator
*
* @param inst the instruction to assemble
*/
private void doAND(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (isByte(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_Reg_Abs_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_Reg_RegDisp_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_Reg_RegOff_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_Reg_RegIdx_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_Reg_RegInd_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitAND_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitAND_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitAND_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitAND_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitAND_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitAND_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitAND_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitAND_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitAND_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitAND_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Test instruction
* and has a BTC operator
*
* @param inst the instruction to assemble
*/
private void doBTC(OPT_Instruction inst) {
if (isImm(MIR_Test.getVal2(inst))) {
if (isReg(MIR_Test.getVal1(inst))) {
emitBTC_Reg_Imm(
getReg(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
emitBTC_Abs_Imm(
getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
emitBTC_RegDisp_Imm(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
emitBTC_RegOff_Imm(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
emitBTC_RegIdx_Imm(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
emitBTC_RegInd_Imm(
getBase(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTC_Reg_Reg(
getReg(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTC_Abs_Reg(
getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTC_RegDisp_Reg(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTC_RegOff_Reg(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTC_RegIdx_Reg(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTC_RegInd_Reg(
getBase(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a FLDL2T operator
*
* @param inst the instruction to assemble
*/
private void doFLDL2T(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitFLDL2T_Reg(
getReg(MIR_Nullary.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a FISTP operator
*
* @param inst the instruction to assemble
*/
private void doFISTP(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_Abs_Reg_Word(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegDisp_Reg_Word(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegOff_Reg_Word(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegIdx_Reg_Word(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegInd_Reg_Word(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isQuad(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_Abs_Reg_Quad(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegDisp_Reg_Quad(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegOff_Reg_Quad(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegIdx_Reg_Quad(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegInd_Reg_Quad(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFISTP_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FDIV operator
*
* @param inst the instruction to assemble
*/
private void doFDIV(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_Abs_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_RegDisp_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_RegOff_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_RegIdx_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_RegInd_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFDIV_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a ROR operator
*
* @param inst the instruction to assemble
*/
private void doROR(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitROR_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitROR_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitROR_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitROR_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitROR_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitROR_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitROR_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitROR_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitROR_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitROR_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROR_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROR_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROR_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROR_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROR_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROR_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROR_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a CVTSS2SD operator
*
* @param inst the instruction to assemble
*/
private void doCVTSS2SD(OPT_Instruction inst) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SD_Reg_Reg(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SD_Reg_Abs(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SD_Reg_RegDisp(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SD_Reg_RegOff(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SD_Reg_RegIdx(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitCVTSS2SD_Reg_RegInd(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a FLDLN2 operator
*
* @param inst the instruction to assemble
*/
private void doFLDLN2(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitFLDLN2_Reg(
getReg(MIR_Nullary.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FIADD operator
*
* @param inst the instruction to assemble
*/
private void doFIADD(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFIADD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a FLD operator
*
* @param inst the instruction to assemble
*/
private void doFLD(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_Abs_Quad(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_RegDisp_Quad(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_RegOff_Quad(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_RegIdx_Quad(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_RegInd_Quad(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_Reg(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_Abs(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_RegDisp(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_RegOff(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_RegIdx(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFLD_Reg_RegInd(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FISUBR operator
*
* @param inst the instruction to assemble
*/
private void doFISUBR(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFISUBR_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a MOVD operator
*
* @param inst the instruction to assemble
*/
private void doMOVD(OPT_Instruction inst) {
if (isReg(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVD_Reg_Reg(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVD_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVD_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVD_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVD_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVD_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a FLDPI operator
*
* @param inst the instruction to assemble
*/
private void doFLDPI(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitFLDPI_Reg(
getReg(MIR_Nullary.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FDIVR operator
*
* @param inst the instruction to assemble
*/
private void doFDIVR(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_Abs_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_RegDisp_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_RegOff_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_RegIdx_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_RegInd_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFDIVR_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a CVTSI2SS operator
*
* @param inst the instruction to assemble
*/
private void doCVTSI2SS(OPT_Instruction inst) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SS_Reg_Reg(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SS_Reg_Abs(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SS_Reg_RegDisp(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SS_Reg_RegOff(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SS_Reg_RegIdx(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitCVTSI2SS_Reg_RegInd(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a POP operator
*
* @param inst the instruction to assemble
*/
private void doPOP(OPT_Instruction inst) {
if (isReg(MIR_Nullary.getResult(inst))) {
emitPOP_Reg(
getReg(MIR_Nullary.getResult(inst)));
} else {
if (isAbs(MIR_Nullary.getResult(inst))) {
emitPOP_Abs(
getDisp(MIR_Nullary.getResult(inst)));
} else {
if (isRegDisp(MIR_Nullary.getResult(inst))) {
emitPOP_RegDisp(
getBase(MIR_Nullary.getResult(inst)), getDisp(MIR_Nullary.getResult(inst)));
} else {
if (isRegOff(MIR_Nullary.getResult(inst))) {
emitPOP_RegOff(
getIndex(MIR_Nullary.getResult(inst)), getScale(MIR_Nullary.getResult(inst)), getDisp(MIR_Nullary.getResult(inst)));
} else {
if (isRegIdx(MIR_Nullary.getResult(inst))) {
emitPOP_RegIdx(
getBase(MIR_Nullary.getResult(inst)), getIndex(MIR_Nullary.getResult(inst)), getScale(MIR_Nullary.getResult(inst)), getDisp(MIR_Nullary.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitPOP_RegInd(
getBase(MIR_Nullary.getResult(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a FILD operator
*
* @param inst the instruction to assemble
*/
private void doFILD(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_Abs_Word(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegDisp_Word(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegOff_Word(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegIdx_Word(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegInd_Word(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isQuad(inst)) {
if (isAbs(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_Abs_Quad(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegDisp_Quad(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegOff_Quad(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegIdx_Quad(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegInd_Quad(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_Abs(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegDisp(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegOff(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegIdx(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFILD_Reg_RegInd(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a MOV operator
*
* @param inst the instruction to assemble
*/
private void doMOV(OPT_Instruction inst) {
if (isReg(MIR_Move.getResult(inst))) {
if (isByte(inst)) {
if (isReg(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Move.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Move.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_Reg_Reg_Byte(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Move.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_Reg_Abs_Byte(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Move.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_Reg_RegDisp_Byte(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Move.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_Reg_RegOff_Byte(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Move.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_Reg_RegIdx_Byte(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Move.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_Reg_RegInd_Byte(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_Move.getValue(inst))) {
emitMOV_Reg_Reg_Word(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getValue(inst))) {
emitMOV_Reg_Abs_Word(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
emitMOV_Reg_RegDisp_Word(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
emitMOV_Reg_RegOff_Word(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
emitMOV_Reg_RegIdx_Word(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_Reg_RegInd_Word(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
}
} else {
if (isImm(MIR_Move.getValue(inst))) {
emitMOV_Reg_Imm(
getReg(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isReg(MIR_Move.getValue(inst))) {
emitMOV_Reg_Reg(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getValue(inst))) {
emitMOV_Reg_Abs(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
emitMOV_Reg_RegDisp(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
emitMOV_Reg_RegOff(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
emitMOV_Reg_RegIdx(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_Reg_RegInd(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_Move.getValue(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
emitMOV_Abs_Imm_Byte(
getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
emitMOV_RegDisp_Imm_Byte(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
emitMOV_RegOff_Imm_Byte(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
emitMOV_RegIdx_Imm_Byte(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitMOV_RegInd_Imm_Byte(
getBase(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
emitMOV_Abs_Imm_Word(
getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
emitMOV_RegDisp_Imm_Word(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
emitMOV_RegOff_Imm_Word(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
emitMOV_RegIdx_Imm_Word(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitMOV_RegInd_Imm_Word(
getBase(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_Move.getResult(inst))) {
emitMOV_Abs_Imm(
getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
emitMOV_RegDisp_Imm(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
emitMOV_RegOff_Imm(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
emitMOV_RegIdx_Imm(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
emitMOV_RegInd_Imm(
getBase(MIR_Move.getResult(inst)),
getImm(MIR_Move.getValue(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Move.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_Abs_Reg_Byte(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Move.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_RegDisp_Reg_Byte(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Move.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_RegOff_Reg_Byte(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Move.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_RegIdx_Reg_Byte(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Move.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitMOV_RegInd_Reg_Byte(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_Abs_Reg_Word(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_RegDisp_Reg_Word(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_RegOff_Reg_Word(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_RegIdx_Reg_Word(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_RegInd_Reg_Word(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOV_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a MOVZX operator
*
* @param inst the instruction to assemble
*/
private void doMOVZX(OPT_Instruction inst) {
if (isByte(inst)) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVZX_Reg_Reg_Byte(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVZX_Reg_Abs_Byte(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVZX_Reg_RegDisp_Byte(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVZX_Reg_RegOff_Byte(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVZX_Reg_RegIdx_Byte(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitMOVZX_Reg_RegInd_Byte(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVZX_Reg_Reg_Word(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVZX_Reg_Abs_Word(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVZX_Reg_RegDisp_Word(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVZX_Reg_RegOff_Word(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVZX_Reg_RegIdx_Word(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVZX_Reg_RegInd_Word(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a FLDL2E operator
*
* @param inst the instruction to assemble
*/
private void doFLDL2E(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitFLDL2E_Reg(
getReg(MIR_Nullary.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPNLTSS operator
*
* @param inst the instruction to assemble
*/
private void doCMPNLTSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPNLTSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a MOVQ operator
*
* @param inst the instruction to assemble
*/
private void doMOVQ(OPT_Instruction inst) {
if (isReg(MIR_Move.getResult(inst))) {
if (isReg(MIR_Move.getValue(inst))) {
emitMOVQ_Reg_Reg(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getValue(inst))) {
emitMOVQ_Reg_Abs(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
emitMOVQ_Reg_RegDisp(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
emitMOVQ_Reg_RegOff(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
emitMOVQ_Reg_RegIdx(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVQ_Reg_RegInd(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
}
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVQ_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVQ_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVQ_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVQ_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVQ_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FSUBRP operator
*
* @param inst the instruction to assemble
*/
private void doFSUBRP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFSUBRP_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_ConvertDW2QW instruction
* and has a CDQ operator
*
* @param inst the instruction to assemble
*/
private void doCDQ(OPT_Instruction inst) {
emitCDQ();
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FPREM operator
*
* @param inst the instruction to assemble
*/
private void doFPREM(OPT_Instruction inst) {
emitFPREM();
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a DIVSD operator
*
* @param inst the instruction to assemble
*/
private void doDIVSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDIVSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitDIVSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Empty instruction
* and has a PAUSE operator
*
* @param inst the instruction to assemble
*/
private void doPAUSE(OPT_Instruction inst) {
emitPAUSE();
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a MOVSS operator
*
* @param inst the instruction to assemble
*/
private void doMOVSS(OPT_Instruction inst) {
if (isReg(MIR_Move.getResult(inst))) {
if (isReg(MIR_Move.getValue(inst))) {
emitMOVSS_Reg_Reg(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getValue(inst))) {
emitMOVSS_Reg_Abs(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
emitMOVSS_Reg_RegDisp(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
emitMOVSS_Reg_RegOff(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
emitMOVSS_Reg_RegIdx(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSS_Reg_RegInd(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
}
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSS_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSS_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSS_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSS_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSS_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_RDTSC instruction
* and has a RDTSC operator
*
* @param inst the instruction to assemble
*/
private void doRDTSC(OPT_Instruction inst) {
emitRDTSC();
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Empty instruction
* and has a FINIT operator
*
* @param inst the instruction to assemble
*/
private void doFINIT(OPT_Instruction inst) {
emitFINIT();
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a MULSD operator
*
* @param inst the instruction to assemble
*/
private void doMULSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitMULSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a CVTTSS2SI operator
*
* @param inst the instruction to assemble
*/
private void doCVTTSS2SI(OPT_Instruction inst) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSS2SI_Reg_Reg(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSS2SI_Reg_Abs(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSS2SI_Reg_RegDisp(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSS2SI_Reg_RegOff(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTTSS2SI_Reg_RegIdx(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitCVTTSS2SI_Reg_RegInd(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_FSave instruction
* and has a FNSAVE operator
*
* @param inst the instruction to assemble
*/
private void doFNSAVE(OPT_Instruction inst) {
if (isAbs(MIR_FSave.getDestination(inst))) {
emitFNSAVE_Abs(
getDisp(MIR_FSave.getDestination(inst)));
} else {
if (isRegDisp(MIR_FSave.getDestination(inst))) {
emitFNSAVE_RegDisp(
getBase(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
} else {
if (isRegOff(MIR_FSave.getDestination(inst))) {
emitFNSAVE_RegOff(
getIndex(MIR_FSave.getDestination(inst)), getScale(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
} else {
if (isRegIdx(MIR_FSave.getDestination(inst))) {
emitFNSAVE_RegIdx(
getBase(MIR_FSave.getDestination(inst)), getIndex(MIR_FSave.getDestination(inst)), getScale(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_FSave.getDestination(inst))) VM._assert(false, inst.toString());
emitFNSAVE_RegInd(
getBase(MIR_FSave.getDestination(inst)));
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a MULSS operator
*
* @param inst the instruction to assemble
*/
private void doMULSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitMULSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitMULSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_CondMove instruction
* and has a CMOV operator
*
* @param inst the instruction to assemble
*/
private void doCMOV(OPT_Instruction inst) {
if (isReg(MIR_CondMove.getValue(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CondMove.getResult(inst))) VM._assert(false, inst.toString());
emitCMOV_Cond_Reg_Reg(
getCond(MIR_CondMove.getCond(inst)),
getReg(MIR_CondMove.getResult(inst)),
getReg(MIR_CondMove.getValue(inst)));
} else {
if (isAbs(MIR_CondMove.getValue(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CondMove.getResult(inst))) VM._assert(false, inst.toString());
emitCMOV_Cond_Reg_Abs(
getCond(MIR_CondMove.getCond(inst)),
getReg(MIR_CondMove.getResult(inst)),
getDisp(MIR_CondMove.getValue(inst)));
} else {
if (isRegDisp(MIR_CondMove.getValue(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CondMove.getResult(inst))) VM._assert(false, inst.toString());
emitCMOV_Cond_Reg_RegDisp(
getCond(MIR_CondMove.getCond(inst)),
getReg(MIR_CondMove.getResult(inst)),
getBase(MIR_CondMove.getValue(inst)), getDisp(MIR_CondMove.getValue(inst)));
} else {
if (isRegOff(MIR_CondMove.getValue(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CondMove.getResult(inst))) VM._assert(false, inst.toString());
emitCMOV_Cond_Reg_RegOff(
getCond(MIR_CondMove.getCond(inst)),
getReg(MIR_CondMove.getResult(inst)),
getIndex(MIR_CondMove.getValue(inst)), getScale(MIR_CondMove.getValue(inst)), getDisp(MIR_CondMove.getValue(inst)));
} else {
if (isRegIdx(MIR_CondMove.getValue(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CondMove.getResult(inst))) VM._assert(false, inst.toString());
emitCMOV_Cond_Reg_RegIdx(
getCond(MIR_CondMove.getCond(inst)),
getReg(MIR_CondMove.getResult(inst)),
getBase(MIR_CondMove.getValue(inst)), getIndex(MIR_CondMove.getValue(inst)), getScale(MIR_CondMove.getValue(inst)), getDisp(MIR_CondMove.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CondMove.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_CondMove.getValue(inst))) VM._assert(false, inst.toString());
emitCMOV_Cond_Reg_RegInd(
getCond(MIR_CondMove.getCond(inst)),
getReg(MIR_CondMove.getResult(inst)),
getBase(MIR_CondMove.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Multiply instruction
* and has a MUL operator
*
* @param inst the instruction to assemble
*/
private void doMUL(OPT_Instruction inst) {
if (isReg(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitMUL_Reg_Reg(
getReg(MIR_Multiply.getResult2(inst)),
getReg(MIR_Multiply.getValue(inst)));
} else {
if (isAbs(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitMUL_Reg_Abs(
getReg(MIR_Multiply.getResult2(inst)),
getDisp(MIR_Multiply.getValue(inst)));
} else {
if (isRegDisp(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitMUL_Reg_RegDisp(
getReg(MIR_Multiply.getResult2(inst)),
getBase(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
} else {
if (isRegOff(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitMUL_Reg_RegOff(
getReg(MIR_Multiply.getResult2(inst)),
getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
} else {
if (isRegIdx(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitMUL_Reg_RegIdx(
getReg(MIR_Multiply.getResult2(inst)),
getBase(MIR_Multiply.getValue(inst)), getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Multiply.getValue(inst))) VM._assert(false, inst.toString());
emitMUL_Reg_RegInd(
getReg(MIR_Multiply.getResult2(inst)),
getBase(MIR_Multiply.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a XORPD operator
*
* @param inst the instruction to assemble
*/
private void doXORPD(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXORPD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Compare instruction
* and has a FUCOMI operator
*
* @param inst the instruction to assemble
*/
private void doFUCOMI(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitFUCOMI_Reg_Reg(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a FIST operator
*
* @param inst the instruction to assemble
*/
private void doFIST(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_Abs_Reg_Word(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_RegDisp_Reg_Word(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_RegOff_Reg_Word(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_RegIdx_Reg_Word(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_RegInd_Reg_Word(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFIST_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FISUB operator
*
* @param inst the instruction to assemble
*/
private void doFISUB(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFISUB_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a XOR operator
*
* @param inst the instruction to assemble
*/
private void doXOR(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (isByte(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_Reg_Abs_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_Reg_RegDisp_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_Reg_RegOff_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_Reg_RegIdx_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_Reg_RegInd_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitXOR_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitXOR_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitXOR_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitXOR_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitXOR_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitXOR_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitXOR_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitXOR_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitXOR_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXOR_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_DoubleShift instruction
* and has a SHLD operator
*
* @param inst the instruction to assemble
*/
private void doSHLD(OPT_Instruction inst) {
if (isImm(MIR_DoubleShift.getBitsToShift(inst))) {
if (isReg(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHLD_Reg_Reg_Imm(
getReg(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isAbs(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHLD_Abs_Reg_Imm(
getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHLD_RegDisp_Reg_Imm(
getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegOff(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHLD_RegOff_Reg_Imm(
getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHLD_RegIdx_Reg_Imm(
getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHLD_RegInd_Reg_Imm(
getBase(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHLD_Reg_Reg_Reg(
getReg(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isAbs(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHLD_Abs_Reg_Reg(
getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHLD_RegDisp_Reg_Reg(
getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegOff(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHLD_RegOff_Reg_Reg(
getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHLD_RegIdx_Reg_Reg(
getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHLD_RegInd_Reg_Reg(
getBase(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Divide instruction
* and has a DIV operator
*
* @param inst the instruction to assemble
*/
private void doDIV(OPT_Instruction inst) {
if (isReg(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitDIV_Reg_Reg(
getReg(MIR_Divide.getResult2(inst)),
getReg(MIR_Divide.getValue(inst)));
} else {
if (isAbs(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitDIV_Reg_Abs(
getReg(MIR_Divide.getResult2(inst)),
getDisp(MIR_Divide.getValue(inst)));
} else {
if (isRegDisp(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitDIV_Reg_RegDisp(
getReg(MIR_Divide.getResult2(inst)),
getBase(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
} else {
if (isRegOff(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitDIV_Reg_RegOff(
getReg(MIR_Divide.getResult2(inst)),
getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
} else {
if (isRegIdx(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitDIV_Reg_RegIdx(
getReg(MIR_Divide.getResult2(inst)),
getBase(MIR_Divide.getValue(inst)), getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Divide.getValue(inst))) VM._assert(false, inst.toString());
emitDIV_Reg_RegInd(
getReg(MIR_Divide.getResult2(inst)),
getBase(MIR_Divide.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Set instruction
* and has a SET operator
*
* @param inst the instruction to assemble
*/
private void doSET(OPT_Instruction inst) {
if (isReg(MIR_Set.getResult(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isByte(inst)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Set.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSET_Cond_Reg_Byte(
getCond(MIR_Set.getCond(inst)),
getReg(MIR_Set.getResult(inst)));
} else {
if (isAbs(MIR_Set.getResult(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isByte(inst)) VM._assert(false, inst.toString());
emitSET_Cond_Abs_Byte(
getCond(MIR_Set.getCond(inst)),
getDisp(MIR_Set.getResult(inst)));
} else {
if (isRegDisp(MIR_Set.getResult(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isByte(inst)) VM._assert(false, inst.toString());
emitSET_Cond_RegDisp_Byte(
getCond(MIR_Set.getCond(inst)),
getBase(MIR_Set.getResult(inst)), getDisp(MIR_Set.getResult(inst)));
} else {
if (isRegOff(MIR_Set.getResult(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isByte(inst)) VM._assert(false, inst.toString());
emitSET_Cond_RegOff_Byte(
getCond(MIR_Set.getCond(inst)),
getIndex(MIR_Set.getResult(inst)), getScale(MIR_Set.getResult(inst)), getDisp(MIR_Set.getResult(inst)));
} else {
if (isRegIdx(MIR_Set.getResult(inst))) {
if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isByte(inst)) VM._assert(false, inst.toString());
emitSET_Cond_RegIdx_Byte(
getCond(MIR_Set.getCond(inst)),
getBase(MIR_Set.getResult(inst)), getIndex(MIR_Set.getResult(inst)), getScale(MIR_Set.getResult(inst)), getDisp(MIR_Set.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Set.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isByte(inst)) VM._assert(false, inst.toString());
emitSET_Cond_RegInd_Byte(
getCond(MIR_Set.getCond(inst)),
getBase(MIR_Set.getResult(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Compare instruction
* and has a UCOMISS operator
*
* @param inst the instruction to assemble
*/
private void doUCOMISS(OPT_Instruction inst) {
if (isReg(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISS_Reg_Reg(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isAbs(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISS_Reg_Abs(
getReg(MIR_Compare.getVal1(inst)),
getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISS_Reg_RegDisp(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISS_Reg_RegOff(
getReg(MIR_Compare.getVal1(inst)),
getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitUCOMISS_Reg_RegIdx(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitUCOMISS_Reg_RegInd(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a RCR operator
*
* @param inst the instruction to assemble
*/
private void doRCR(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitRCR_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitRCR_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitRCR_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitRCR_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitRCR_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitRCR_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitRCR_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitRCR_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitRCR_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitRCR_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCR_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCR_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCR_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCR_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCR_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCR_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCR_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Return instruction
* and has a RET operator
*
* @param inst the instruction to assemble
*/
private void doRET(OPT_Instruction inst) {
if (isImm(MIR_Return.getPopBytes(inst))) {
emitRET_Imm(
getImm(MIR_Return.getPopBytes(inst)));
} else {
emitRET();
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a ADD operator
*
* @param inst the instruction to assemble
*/
private void doADD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (isByte(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_Reg_Abs_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_Reg_RegDisp_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_Reg_RegOff_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_Reg_RegIdx_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_Reg_RegInd_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitADD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitADD_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADD_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitADD_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADD_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitADD_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitADD_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADD_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADD_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADD_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryAcc instruction
* and has a FCHS operator
*
* @param inst the instruction to assemble
*/
private void doFCHS(OPT_Instruction inst) {
emitFCHS();
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a SAR operator
*
* @param inst the instruction to assemble
*/
private void doSAR(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSAR_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSAR_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSAR_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitSAR_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSAR_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSAR_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitSAR_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSAR_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSAR_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSAR_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAR_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAR_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAR_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAR_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAR_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAR_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAR_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPLESS operator
*
* @param inst the instruction to assemble
*/
private void doCMPLESS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPLESS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPORDSD operator
*
* @param inst the instruction to assemble
*/
private void doCMPORDSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPORDSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_CondMove instruction
* and has a FCMOV operator
*
* @param inst the instruction to assemble
*/
private void doFCMOV(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CondMove.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CondMove.getValue(inst))) VM._assert(false, inst.toString());
emitFCMOV_Cond_Reg_Reg(
getCond(MIR_CondMove.getCond(inst)),
getReg(MIR_CondMove.getResult(inst)),
getReg(MIR_CondMove.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FSUB operator
*
* @param inst the instruction to assemble
*/
private void doFSUB(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_Abs_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_RegDisp_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_RegOff_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_RegIdx_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_RegInd_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFSUB_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a SHL operator
*
* @param inst the instruction to assemble
*/
private void doSHL(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSHL_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSHL_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSHL_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitSHL_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSHL_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSHL_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitSHL_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSHL_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSHL_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSHL_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHL_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHL_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHL_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHL_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHL_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSHL_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSHL_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a FSTP operator
*
* @param inst the instruction to assemble
*/
private void doFSTP(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_Abs_Reg_Quad(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_RegDisp_Reg_Quad(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_RegOff_Reg_Quad(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_RegIdx_Reg_Quad(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_RegInd_Reg_Quad(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_Reg_Reg(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFSTP_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a ROL operator
*
* @param inst the instruction to assemble
*/
private void doROL(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitROL_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitROL_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitROL_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitROL_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitROL_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitROL_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitROL_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitROL_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitROL_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitROL_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROL_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROL_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROL_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROL_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROL_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitROL_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitROL_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryAcc instruction
* and has a INC operator
*
* @param inst the instruction to assemble
*/
private void doINC(OPT_Instruction inst) {
if (isByte(inst)) {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_UnaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitINC_Reg_Byte(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitINC_Abs_Byte(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegDisp_Byte(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegOff_Byte(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegIdx_Byte(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitINC_RegInd_Byte(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
emitINC_Reg_Word(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitINC_Abs_Word(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegDisp_Word(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegOff_Word(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegIdx_Word(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitINC_RegInd_Word(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
emitINC_Reg(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitINC_Abs(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegDisp(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegOff(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitINC_RegIdx(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitINC_RegInd(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FIDIVR operator
*
* @param inst the instruction to assemble
*/
private void doFIDIVR(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFIDIVR_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a MOVSD operator
*
* @param inst the instruction to assemble
*/
private void doMOVSD(OPT_Instruction inst) {
if (isReg(MIR_Move.getResult(inst))) {
if (isReg(MIR_Move.getValue(inst))) {
emitMOVSD_Reg_Reg(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getValue(inst))) {
emitMOVSD_Reg_Abs(
getReg(MIR_Move.getResult(inst)),
getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getValue(inst))) {
emitMOVSD_Reg_RegDisp(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getValue(inst))) {
emitMOVSD_Reg_RegOff(
getReg(MIR_Move.getResult(inst)),
getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getValue(inst))) {
emitMOVSD_Reg_RegIdx(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSD_Reg_RegInd(
getReg(MIR_Move.getResult(inst)),
getBase(MIR_Move.getValue(inst)));
}
}
}
}
}
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSD_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSD_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSD_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSD_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitMOVSD_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a CVTSD2SI operator
*
* @param inst the instruction to assemble
*/
private void doCVTSD2SI(OPT_Instruction inst) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SI_Reg_Reg(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SI_Reg_Abs(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SI_Reg_RegDisp(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SI_Reg_RegOff(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SI_Reg_RegIdx(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitCVTSD2SI_Reg_RegInd(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a ADC operator
*
* @param inst the instruction to assemble
*/
private void doADC(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (isByte(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_Reg_Abs_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_Reg_RegDisp_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_Reg_RegOff_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_Reg_RegIdx_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_Reg_RegInd_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitADC_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitADC_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADC_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitADC_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADC_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitADC_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitADC_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADC_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitADC_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADC_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a XORPS operator
*
* @param inst the instruction to assemble
*/
private void doXORPS(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitXORPS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Test instruction
* and has a BTS operator
*
* @param inst the instruction to assemble
*/
private void doBTS(OPT_Instruction inst) {
if (isImm(MIR_Test.getVal2(inst))) {
if (isReg(MIR_Test.getVal1(inst))) {
emitBTS_Reg_Imm(
getReg(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
emitBTS_Abs_Imm(
getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
emitBTS_RegDisp_Imm(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
emitBTS_RegOff_Imm(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
emitBTS_RegIdx_Imm(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
emitBTS_RegInd_Imm(
getBase(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTS_Reg_Reg(
getReg(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTS_Abs_Reg(
getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTS_RegDisp_Reg(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTS_RegOff_Reg(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTS_RegIdx_Reg(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTS_RegInd_Reg(
getBase(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryNoRes instruction
* and has a PUSH operator
*
* @param inst the instruction to assemble
*/
private void doPUSH(OPT_Instruction inst) {
if (isImm(MIR_UnaryNoRes.getVal(inst))) {
emitPUSH_Imm(
getImm(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isReg(MIR_UnaryNoRes.getVal(inst))) {
emitPUSH_Reg(
getReg(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isAbs(MIR_UnaryNoRes.getVal(inst))) {
emitPUSH_Abs(
getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegDisp(MIR_UnaryNoRes.getVal(inst))) {
emitPUSH_RegDisp(
getBase(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegOff(MIR_UnaryNoRes.getVal(inst))) {
emitPUSH_RegOff(
getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegIdx(MIR_UnaryNoRes.getVal(inst))) {
emitPUSH_RegIdx(
getBase(MIR_UnaryNoRes.getVal(inst)), getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryNoRes.getVal(inst))) VM._assert(false, inst.toString());
emitPUSH_RegInd(
getBase(MIR_UnaryNoRes.getVal(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Divide instruction
* and has a IDIV operator
*
* @param inst the instruction to assemble
*/
private void doIDIV(OPT_Instruction inst) {
if (isReg(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitIDIV_Reg_Reg(
getReg(MIR_Divide.getResult2(inst)),
getReg(MIR_Divide.getValue(inst)));
} else {
if (isAbs(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitIDIV_Reg_Abs(
getReg(MIR_Divide.getResult2(inst)),
getDisp(MIR_Divide.getValue(inst)));
} else {
if (isRegDisp(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitIDIV_Reg_RegDisp(
getReg(MIR_Divide.getResult2(inst)),
getBase(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
} else {
if (isRegOff(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitIDIV_Reg_RegOff(
getReg(MIR_Divide.getResult2(inst)),
getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
} else {
if (isRegIdx(MIR_Divide.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
emitIDIV_Reg_RegIdx(
getReg(MIR_Divide.getResult2(inst)),
getBase(MIR_Divide.getValue(inst)), getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Divide.getResult2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Divide.getValue(inst))) VM._assert(false, inst.toString());
emitIDIV_Reg_RegInd(
getReg(MIR_Divide.getResult2(inst)),
getBase(MIR_Divide.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPNLESS operator
*
* @param inst the instruction to assemble
*/
private void doCMPNLESS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPNLESS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPEQSD operator
*
* @param inst the instruction to assemble
*/
private void doCMPEQSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPEQSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPEQSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Lea instruction
* and has a LEA operator
*
* @param inst the instruction to assemble
*/
private void doLEA(OPT_Instruction inst) {
if (isAbs(MIR_Lea.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Lea.getResult(inst))) VM._assert(false, inst.toString());
emitLEA_Reg_Abs(
getReg(MIR_Lea.getResult(inst)),
getDisp(MIR_Lea.getValue(inst)));
} else {
if (isRegDisp(MIR_Lea.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Lea.getResult(inst))) VM._assert(false, inst.toString());
emitLEA_Reg_RegDisp(
getReg(MIR_Lea.getResult(inst)),
getBase(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
} else {
if (isRegOff(MIR_Lea.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Lea.getResult(inst))) VM._assert(false, inst.toString());
emitLEA_Reg_RegOff(
getReg(MIR_Lea.getResult(inst)),
getIndex(MIR_Lea.getValue(inst)), getScale(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
} else {
if (isRegIdx(MIR_Lea.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Lea.getResult(inst))) VM._assert(false, inst.toString());
emitLEA_Reg_RegIdx(
getReg(MIR_Lea.getResult(inst)),
getBase(MIR_Lea.getValue(inst)), getIndex(MIR_Lea.getValue(inst)), getScale(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Lea.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Lea.getValue(inst))) VM._assert(false, inst.toString());
emitLEA_Reg_RegInd(
getReg(MIR_Lea.getResult(inst)),
getBase(MIR_Lea.getValue(inst)));
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_CompareExchange instruction
* and has a CMPXCHG operator
*
* @param inst the instruction to assemble
*/
private void doCMPXCHG(OPT_Instruction inst) {
if (isReg(MIR_CompareExchange.getMemAddr(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_CompareExchange.getNewValue(inst))) VM._assert(false, inst.toString());
emitCMPXCHG_Reg_Reg(
getReg(MIR_CompareExchange.getMemAddr(inst)),
getReg(MIR_CompareExchange.getNewValue(inst)));
} else {
if (isAbs(MIR_CompareExchange.getMemAddr(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_CompareExchange.getNewValue(inst))) VM._assert(false, inst.toString());
emitCMPXCHG_Abs_Reg(
getDisp(MIR_CompareExchange.getMemAddr(inst)),
getReg(MIR_CompareExchange.getNewValue(inst)));
} else {
if (isRegDisp(MIR_CompareExchange.getMemAddr(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_CompareExchange.getNewValue(inst))) VM._assert(false, inst.toString());
emitCMPXCHG_RegDisp_Reg(
getBase(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
getReg(MIR_CompareExchange.getNewValue(inst)));
} else {
if (isRegOff(MIR_CompareExchange.getMemAddr(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_CompareExchange.getNewValue(inst))) VM._assert(false, inst.toString());
emitCMPXCHG_RegOff_Reg(
getIndex(MIR_CompareExchange.getMemAddr(inst)), getScale(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
getReg(MIR_CompareExchange.getNewValue(inst)));
} else {
if (isRegIdx(MIR_CompareExchange.getMemAddr(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_CompareExchange.getNewValue(inst))) VM._assert(false, inst.toString());
emitCMPXCHG_RegIdx_Reg(
getBase(MIR_CompareExchange.getMemAddr(inst)), getIndex(MIR_CompareExchange.getMemAddr(inst)), getScale(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
getReg(MIR_CompareExchange.getNewValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_CompareExchange.getMemAddr(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_CompareExchange.getNewValue(inst))) VM._assert(false, inst.toString());
emitCMPXCHG_RegInd_Reg(
getBase(MIR_CompareExchange.getMemAddr(inst)),
getReg(MIR_CompareExchange.getNewValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a OR operator
*
* @param inst the instruction to assemble
*/
private void doOR(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (isByte(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_Reg_Abs_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_Reg_RegDisp_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_Reg_RegOff_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_Reg_RegIdx_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_Reg_RegInd_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitOR_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitOR_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitOR_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitOR_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitOR_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitOR_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitOR_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitOR_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitOR_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitOR_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Compare instruction
* and has a CMP operator
*
* @param inst the instruction to assemble
*/
private void doCMP(OPT_Instruction inst) {
if (isReg(MIR_Compare.getVal1(inst))) {
if (isByte(inst)) {
if (isImm(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_Reg_Imm_Byte(
getReg(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isReg(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_Reg_Reg_Byte(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isAbs(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_Reg_Abs_Byte(
getReg(MIR_Compare.getVal1(inst)),
getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_Reg_RegDisp_Byte(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_Reg_RegOff_Byte(
getReg(MIR_Compare.getVal1(inst)),
getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal2(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_Reg_RegIdx_Byte(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_Reg_RegInd_Byte(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)));
}
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isImm(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_Imm_Word(
getReg(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isReg(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_Reg_Word(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isAbs(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_Abs_Word(
getReg(MIR_Compare.getVal1(inst)),
getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_RegDisp_Word(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_RegOff_Word(
getReg(MIR_Compare.getVal1(inst)),
getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_RegIdx_Word(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_Reg_RegInd_Word(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)));
}
}
}
}
}
}
} else {
if (isImm(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_Imm(
getReg(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isReg(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_Reg(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isAbs(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_Abs(
getReg(MIR_Compare.getVal1(inst)),
getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_RegDisp(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_RegOff(
getReg(MIR_Compare.getVal1(inst)),
getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal2(inst))) {
emitCMP_Reg_RegIdx(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_Reg_RegInd(
getReg(MIR_Compare.getVal1(inst)),
getBase(MIR_Compare.getVal2(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_Compare.getVal2(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_Compare.getVal1(inst))) {
emitCMP_Abs_Imm_Byte(
getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal1(inst))) {
emitCMP_RegDisp_Imm_Byte(
getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal1(inst))) {
emitCMP_RegOff_Imm_Byte(
getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal1(inst))) {
emitCMP_RegIdx_Imm_Byte(
getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitCMP_RegInd_Imm_Byte(
getBase(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_Compare.getVal1(inst))) {
emitCMP_Abs_Imm_Word(
getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal1(inst))) {
emitCMP_RegDisp_Imm_Word(
getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal1(inst))) {
emitCMP_RegOff_Imm_Word(
getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal1(inst))) {
emitCMP_RegIdx_Imm_Word(
getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitCMP_RegInd_Imm_Word(
getBase(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
}
}
}
}
} else {
if (isAbs(MIR_Compare.getVal1(inst))) {
emitCMP_Abs_Imm(
getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal1(inst))) {
emitCMP_RegDisp_Imm(
getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal1(inst))) {
emitCMP_RegOff_Imm(
getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal1(inst))) {
emitCMP_RegIdx_Imm(
getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
emitCMP_RegInd_Imm(
getBase(MIR_Compare.getVal1(inst)),
getImm(MIR_Compare.getVal2(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_Abs_Reg_Byte(
getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_RegDisp_Reg_Byte(
getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_RegOff_Reg_Byte(
getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_RegIdx_Reg_Byte(
getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Compare.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitCMP_RegInd_Reg_Byte(
getBase(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_Abs_Reg_Word(
getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_RegDisp_Reg_Word(
getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_RegOff_Reg_Word(
getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_RegIdx_Reg_Word(
getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_RegInd_Reg_Word(
getBase(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
}
}
}
}
} else {
if (isAbs(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_Abs_Reg(
getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegDisp(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_RegDisp_Reg(
getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegOff(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_RegOff_Reg(
getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (isRegIdx(MIR_Compare.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_RegIdx_Reg(
getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitCMP_RegInd_Reg(
getBase(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a IMUL2 operator
*
* @param inst the instruction to assemble
*/
private void doIMUL2(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitIMUL2_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitIMUL2_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitIMUL2_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitIMUL2_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitIMUL2_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitIMUL2_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitIMUL2_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPLTSS operator
*
* @param inst the instruction to assemble
*/
private void doCMPLTSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPLTSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FDIVRP operator
*
* @param inst the instruction to assemble
*/
private void doFDIVRP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFDIVRP_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPUNORDSD operator
*
* @param inst the instruction to assemble
*/
private void doCMPUNORDSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a ADDSD operator
*
* @param inst the instruction to assemble
*/
private void doADDSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADDSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_DoubleShift instruction
* and has a SHRD operator
*
* @param inst the instruction to assemble
*/
private void doSHRD(OPT_Instruction inst) {
if (isImm(MIR_DoubleShift.getBitsToShift(inst))) {
if (isReg(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHRD_Reg_Reg_Imm(
getReg(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isAbs(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHRD_Abs_Reg_Imm(
getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHRD_RegDisp_Reg_Imm(
getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegOff(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHRD_RegOff_Reg_Imm(
getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHRD_RegIdx_Reg_Imm(
getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
emitSHRD_RegInd_Reg_Imm(
getBase(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getImm(MIR_DoubleShift.getBitsToShift(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHRD_Reg_Reg_Reg(
getReg(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isAbs(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHRD_Abs_Reg_Reg(
getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHRD_RegDisp_Reg_Reg(
getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegOff(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHRD_RegOff_Reg_Reg(
getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHRD_RegIdx_Reg_Reg(
getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getSource(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(false, inst.toString());
emitSHRD_RegInd_Reg_Reg(
getBase(MIR_DoubleShift.getResult(inst)),
getReg(MIR_DoubleShift.getSource(inst)),
getReg(MIR_DoubleShift.getBitsToShift(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_FSave instruction
* and has a FRSTOR operator
*
* @param inst the instruction to assemble
*/
private void doFRSTOR(OPT_Instruction inst) {
if (isAbs(MIR_FSave.getDestination(inst))) {
emitFRSTOR_Abs(
getDisp(MIR_FSave.getDestination(inst)));
} else {
if (isRegDisp(MIR_FSave.getDestination(inst))) {
emitFRSTOR_RegDisp(
getBase(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
} else {
if (isRegOff(MIR_FSave.getDestination(inst))) {
emitFRSTOR_RegOff(
getIndex(MIR_FSave.getDestination(inst)), getScale(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
} else {
if (isRegIdx(MIR_FSave.getDestination(inst))) {
emitFRSTOR_RegIdx(
getBase(MIR_FSave.getDestination(inst)), getIndex(MIR_FSave.getDestination(inst)), getScale(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_FSave.getDestination(inst))) VM._assert(false, inst.toString());
emitFRSTOR_RegInd(
getBase(MIR_FSave.getDestination(inst)));
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryAcc instruction
* and has a BSWAP operator
*
* @param inst the instruction to assemble
*/
private void doBSWAP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitBSWAP_Reg(
getReg(MIR_UnaryAcc.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Trap instruction
* and has a INT operator
*
* @param inst the instruction to assemble
*/
private void doINT(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isImm(MIR_Trap.getTrapCode(inst))) VM._assert(false, inst.toString());
emitINT_Imm(
getImm(MIR_Trap.getTrapCode(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPNLTSD operator
*
* @param inst the instruction to assemble
*/
private void doCMPNLTSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLTSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPNLTSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPUNORDSS operator
*
* @param inst the instruction to assemble
*/
private void doCMPUNORDSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPUNORDSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a CVTSI2SD operator
*
* @param inst the instruction to assemble
*/
private void doCVTSI2SD(OPT_Instruction inst) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SD_Reg_Reg(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SD_Reg_Abs(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SD_Reg_RegDisp(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SD_Reg_RegOff(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSI2SD_Reg_RegIdx(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitCVTSI2SD_Reg_RegInd(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FSUBR operator
*
* @param inst the instruction to assemble
*/
private void doFSUBR(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_Abs_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_RegDisp_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_RegOff_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_RegIdx_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_RegInd_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFSUBR_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a SBB operator
*
* @param inst the instruction to assemble
*/
private void doSBB(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (isByte(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_Reg_Abs_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_Reg_RegDisp_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_Reg_RegOff_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_Reg_RegIdx_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_Reg_RegInd_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitSBB_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSBB_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSBB_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSBB_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSBB_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSBB_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSBB_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSBB_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSBB_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSBB_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPNESS operator
*
* @param inst the instruction to assemble
*/
private void doCMPNESS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNESS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPNESS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a FLDLG2 operator
*
* @param inst the instruction to assemble
*/
private void doFLDLG2(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitFLDLG2_Reg(
getReg(MIR_Nullary.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryNoRes instruction
* and has a FNSTCW operator
*
* @param inst the instruction to assemble
*/
private void doFNSTCW(OPT_Instruction inst) {
if (isAbs(MIR_UnaryNoRes.getVal(inst))) {
emitFNSTCW_Abs(
getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegDisp(MIR_UnaryNoRes.getVal(inst))) {
emitFNSTCW_RegDisp(
getBase(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegOff(MIR_UnaryNoRes.getVal(inst))) {
emitFNSTCW_RegOff(
getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegIdx(MIR_UnaryNoRes.getVal(inst))) {
emitFNSTCW_RegIdx(
getBase(MIR_UnaryNoRes.getVal(inst)), getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryNoRes.getVal(inst))) VM._assert(false, inst.toString());
emitFNSTCW_RegInd(
getBase(MIR_UnaryNoRes.getVal(inst)));
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_CacheOp instruction
* and has a PREFETCHNTA operator
*
* @param inst the instruction to assemble
*/
private void doPREFETCHNTA(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_CacheOp.getAddress(inst))) VM._assert(false, inst.toString());
emitPREFETCHNTA_Reg(
getReg(MIR_CacheOp.getAddress(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FIDIV operator
*
* @param inst the instruction to assemble
*/
private void doFIDIV(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFIDIV_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPLTSD operator
*
* @param inst the instruction to assemble
*/
private void doCMPLTSD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLTSD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPLTSD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a SAL operator
*
* @param inst the instruction to assemble
*/
private void doSAL(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSAL_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSAL_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSAL_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitSAL_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSAL_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSAL_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitSAL_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSAL_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSAL_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSAL_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAL_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAL_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAL_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAL_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAL_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSAL_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSAL_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Compare instruction
* and has a FUCOMIP operator
*
* @param inst the instruction to assemble
*/
private void doFUCOMIP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Compare.getVal2(inst))) VM._assert(false, inst.toString());
emitFUCOMIP_Reg_Reg(
getReg(MIR_Compare.getVal1(inst)),
getReg(MIR_Compare.getVal2(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Test instruction
* and has a BT operator
*
* @param inst the instruction to assemble
*/
private void doBT(OPT_Instruction inst) {
if (isImm(MIR_Test.getVal2(inst))) {
if (isReg(MIR_Test.getVal1(inst))) {
emitBT_Reg_Imm(
getReg(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
emitBT_Abs_Imm(
getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
emitBT_RegDisp_Imm(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
emitBT_RegOff_Imm(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
emitBT_RegIdx_Imm(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
emitBT_RegInd_Imm(
getBase(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBT_Reg_Reg(
getReg(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBT_Abs_Reg(
getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBT_RegDisp_Reg(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBT_RegOff_Reg(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBT_RegIdx_Reg(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBT_RegInd_Reg(
getBase(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FADDP operator
*
* @param inst the instruction to assemble
*/
private void doFADDP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFADDP_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a FLD1 operator
*
* @param inst the instruction to assemble
*/
private void doFLD1(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitFLD1_Reg(
getReg(MIR_Nullary.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Move instruction
* and has a FST operator
*
* @param inst the instruction to assemble
*/
private void doFST(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_Abs_Reg_Quad(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_RegDisp_Reg_Quad(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_RegOff_Reg_Quad(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_RegIdx_Reg_Quad(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_RegInd_Reg_Quad(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_Reg_Reg(
getReg(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isAbs(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_Abs_Reg(
getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegDisp(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_RegDisp_Reg(
getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegOff(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_RegOff_Reg(
getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (isRegIdx(MIR_Move.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_RegIdx_Reg(
getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Move.getValue(inst))) VM._assert(false, inst.toString());
emitFST_RegInd_Reg(
getBase(MIR_Move.getResult(inst)),
getReg(MIR_Move.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Empty instruction
* and has a FNINIT operator
*
* @param inst the instruction to assemble
*/
private void doFNINIT(OPT_Instruction inst) {
emitFNINIT();
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPORDSS operator
*
* @param inst the instruction to assemble
*/
private void doCMPORDSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPORDSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPORDSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_CaseLabel instruction
* and has a OFFSET operator
*
* @param inst the instruction to assemble
*/
private void doOFFSET(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isImm(MIR_CaseLabel.getIndex(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isImmOrLabel(MIR_CaseLabel.getTarget(inst))) VM._assert(false, inst.toString());
emitOFFSET_Imm_ImmOrLabel(
getImm(MIR_CaseLabel.getIndex(inst)),
getImm(MIR_CaseLabel.getTarget(inst)), getLabel(MIR_CaseLabel.getTarget(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_XChng instruction
* and has a FXCH operator
*
* @param inst the instruction to assemble
*/
private void doFXCH(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_XChng.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_XChng.getVal2(inst))) VM._assert(false, inst.toString());
emitFXCH_Reg_Reg(
getReg(MIR_XChng.getVal1(inst)),
getReg(MIR_XChng.getVal2(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Multiply instruction
* and has a IMUL1 operator
*
* @param inst the instruction to assemble
*/
private void doIMUL1(OPT_Instruction inst) {
if (isReg(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitIMUL1_Reg_Reg(
getReg(MIR_Multiply.getResult2(inst)),
getReg(MIR_Multiply.getValue(inst)));
} else {
if (isAbs(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitIMUL1_Reg_Abs(
getReg(MIR_Multiply.getResult2(inst)),
getDisp(MIR_Multiply.getValue(inst)));
} else {
if (isRegDisp(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitIMUL1_Reg_RegDisp(
getReg(MIR_Multiply.getResult2(inst)),
getBase(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
} else {
if (isRegOff(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitIMUL1_Reg_RegOff(
getReg(MIR_Multiply.getResult2(inst)),
getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
} else {
if (isRegIdx(MIR_Multiply.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
emitIMUL1_Reg_RegIdx(
getReg(MIR_Multiply.getResult2(inst)),
getBase(MIR_Multiply.getValue(inst)), getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Multiply.getResult2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Multiply.getValue(inst))) VM._assert(false, inst.toString());
emitIMUL1_Reg_RegInd(
getReg(MIR_Multiply.getResult2(inst)),
getBase(MIR_Multiply.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FSUBP operator
*
* @param inst the instruction to assemble
*/
private void doFSUBP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFSUBP_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a ADDSS operator
*
* @param inst the instruction to assemble
*/
private void doADDSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitADDSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitADDSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Test instruction
* and has a BTR operator
*
* @param inst the instruction to assemble
*/
private void doBTR(OPT_Instruction inst) {
if (isImm(MIR_Test.getVal2(inst))) {
if (isReg(MIR_Test.getVal1(inst))) {
emitBTR_Reg_Imm(
getReg(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
emitBTR_Abs_Imm(
getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
emitBTR_RegDisp_Imm(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
emitBTR_RegOff_Imm(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
emitBTR_RegIdx_Imm(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
emitBTR_RegInd_Imm(
getBase(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTR_Reg_Reg(
getReg(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTR_Abs_Reg(
getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTR_RegDisp_Reg(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTR_RegOff_Reg(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTR_RegIdx_Reg(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitBTR_RegInd_Reg(
getBase(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a SUBSS operator
*
* @param inst the instruction to assemble
*/
private void doSUBSS(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSS_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSS_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSS_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSS_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUBSS_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUBSS_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a FFREE operator
*
* @param inst the instruction to assemble
*/
private void doFFREE(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitFFREE_Reg(
getReg(MIR_Nullary.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a RCL operator
*
* @param inst the instruction to assemble
*/
private void doRCL(OPT_Instruction inst) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitRCL_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitRCL_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitRCL_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitRCL_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitRCL_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitRCL_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
emitRCL_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitRCL_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitRCL_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitRCL_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCL_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCL_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCL_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCL_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCL_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitRCL_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitRCL_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPLESD operator
*
* @param inst the instruction to assemble
*/
private void doCMPLESD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPLESD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPLESD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryNoRes instruction
* and has a FLDCW operator
*
* @param inst the instruction to assemble
*/
private void doFLDCW(OPT_Instruction inst) {
if (isAbs(MIR_UnaryNoRes.getVal(inst))) {
emitFLDCW_Abs(
getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegDisp(MIR_UnaryNoRes.getVal(inst))) {
emitFLDCW_RegDisp(
getBase(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegOff(MIR_UnaryNoRes.getVal(inst))) {
emitFLDCW_RegOff(
getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegIdx(MIR_UnaryNoRes.getVal(inst))) {
emitFLDCW_RegIdx(
getBase(MIR_UnaryNoRes.getVal(inst)), getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryNoRes.getVal(inst))) VM._assert(false, inst.toString());
emitFLDCW_RegInd(
getBase(MIR_UnaryNoRes.getVal(inst)));
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FIMUL operator
*
* @param inst the instruction to assemble
*/
private void doFIMUL(OPT_Instruction inst) {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFIMUL_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryAcc instruction
* and has a DEC operator
*
* @param inst the instruction to assemble
*/
private void doDEC(OPT_Instruction inst) {
if (isByte(inst)) {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_UnaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitDEC_Reg_Byte(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitDEC_Abs_Byte(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegDisp_Byte(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegOff_Byte(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegIdx_Byte(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDEC_RegInd_Byte(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
emitDEC_Reg_Word(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitDEC_Abs_Word(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegDisp_Word(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegOff_Word(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegIdx_Word(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDEC_RegInd_Word(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
emitDEC_Reg(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitDEC_Abs(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegDisp(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegOff(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitDEC_RegIdx(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitDEC_RegInd(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FMUL operator
*
* @param inst the instruction to assemble
*/
private void doFMUL(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_Abs_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_RegDisp_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_RegOff_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_RegIdx_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_RegInd_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFMUL_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FADD operator
*
* @param inst the instruction to assemble
*/
private void doFADD(OPT_Instruction inst) {
if (isQuad(inst)) {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_Abs_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_RegDisp_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_RegOff_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_RegIdx_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_RegInd_Quad(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFADD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Call instruction
* and has a CALL operator
*
* @param inst the instruction to assemble
*/
private void doCALL(OPT_Instruction inst) {
if (isImm(MIR_Call.getTarget(inst))) {
emitCALL_Imm(
getImm(MIR_Call.getTarget(inst)));
} else {
if (isReg(MIR_Call.getTarget(inst))) {
emitCALL_Reg(
getReg(MIR_Call.getTarget(inst)));
} else {
if (isAbs(MIR_Call.getTarget(inst))) {
emitCALL_Abs(
getDisp(MIR_Call.getTarget(inst)));
} else {
if (isRegDisp(MIR_Call.getTarget(inst))) {
emitCALL_RegDisp(
getBase(MIR_Call.getTarget(inst)), getDisp(MIR_Call.getTarget(inst)));
} else {
if (isRegOff(MIR_Call.getTarget(inst))) {
emitCALL_RegOff(
getIndex(MIR_Call.getTarget(inst)), getScale(MIR_Call.getTarget(inst)), getDisp(MIR_Call.getTarget(inst)));
} else {
if (isRegIdx(MIR_Call.getTarget(inst))) {
emitCALL_RegIdx(
getBase(MIR_Call.getTarget(inst)), getIndex(MIR_Call.getTarget(inst)), getScale(MIR_Call.getTarget(inst)), getDisp(MIR_Call.getTarget(inst)));
} else {
if (isRegInd(MIR_Call.getTarget(inst))) {
emitCALL_RegInd(
getBase(MIR_Call.getTarget(inst)));
} else {
if (isLabel(MIR_Call.getTarget(inst))) {
emitCALL_Label(
getLabel(MIR_Call.getTarget(inst)));
} else {
if (VM.VerifyAssertions && !isImmOrLabel(MIR_Call.getTarget(inst))) VM._assert(false, inst.toString());
emitCALL_ImmOrLabel(
getImm(MIR_Call.getTarget(inst)), getLabel(MIR_Call.getTarget(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryNoRes instruction
* and has a FSTCW operator
*
* @param inst the instruction to assemble
*/
private void doFSTCW(OPT_Instruction inst) {
if (isAbs(MIR_UnaryNoRes.getVal(inst))) {
emitFSTCW_Abs(
getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegDisp(MIR_UnaryNoRes.getVal(inst))) {
emitFSTCW_RegDisp(
getBase(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegOff(MIR_UnaryNoRes.getVal(inst))) {
emitFSTCW_RegOff(
getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (isRegIdx(MIR_UnaryNoRes.getVal(inst))) {
emitFSTCW_RegIdx(
getBase(MIR_UnaryNoRes.getVal(inst)), getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryNoRes.getVal(inst))) VM._assert(false, inst.toString());
emitFSTCW_RegInd(
getBase(MIR_UnaryNoRes.getVal(inst)));
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a CVTSD2SS operator
*
* @param inst the instruction to assemble
*/
private void doCVTSD2SS(OPT_Instruction inst) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SS_Reg_Reg(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SS_Reg_Abs(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SS_Reg_RegDisp(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SS_Reg_RegOff(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSD2SS_Reg_RegIdx(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitCVTSD2SS_Reg_RegInd(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a CMPNLESD operator
*
* @param inst the instruction to assemble
*/
private void doCMPNLESD(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESD_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESD_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESD_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESD_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitCMPNLESD_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitCMPNLESD_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Test instruction
* and has a TEST operator
*
* @param inst the instruction to assemble
*/
private void doTEST(OPT_Instruction inst) {
if (isImm(MIR_Test.getVal2(inst))) {
if (isByte(inst)) {
if (isReg(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_Test.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
emitTEST_Reg_Imm_Byte(
getReg(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
emitTEST_Abs_Imm_Byte(
getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
emitTEST_RegDisp_Imm_Byte(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
emitTEST_RegOff_Imm_Byte(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
emitTEST_RegIdx_Imm_Byte(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
emitTEST_RegInd_Imm_Byte(
getBase(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_Test.getVal1(inst))) {
emitTEST_Reg_Imm_Word(
getReg(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
emitTEST_Abs_Imm_Word(
getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
emitTEST_RegDisp_Imm_Word(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
emitTEST_RegOff_Imm_Word(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
emitTEST_RegIdx_Imm_Word(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
emitTEST_RegInd_Imm_Word(
getBase(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_Test.getVal1(inst))) {
emitTEST_Reg_Imm(
getReg(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
emitTEST_Abs_Imm(
getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
emitTEST_RegDisp_Imm(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
emitTEST_RegOff_Imm(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
emitTEST_RegIdx_Imm(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
emitTEST_RegInd_Imm(
getBase(MIR_Test.getVal1(inst)),
getImm(MIR_Test.getVal2(inst)));
}
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isReg(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Test.getVal1(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Test.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitTEST_Reg_Reg_Byte(
getReg(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Test.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitTEST_Abs_Reg_Byte(
getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Test.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitTEST_RegDisp_Reg_Byte(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Test.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitTEST_RegOff_Reg_Byte(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Test.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitTEST_RegIdx_Reg_Byte(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_Test.getVal2(inst)) < 4)) VM._assert(false, inst.toString());
emitTEST_RegInd_Reg_Byte(
getBase(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_Reg_Reg_Word(
getReg(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_Abs_Reg_Word(
getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_RegDisp_Reg_Word(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_RegOff_Reg_Word(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_RegIdx_Reg_Word(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_RegInd_Reg_Word(
getBase(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_Reg_Reg(
getReg(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isAbs(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_Abs_Reg(
getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegDisp(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_RegDisp_Reg(
getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegOff(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_RegOff_Reg(
getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (isRegIdx(MIR_Test.getVal1(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_RegIdx_Reg(
getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_Test.getVal2(inst))) VM._assert(false, inst.toString());
emitTEST_RegInd_Reg(
getBase(MIR_Test.getVal1(inst)),
getReg(MIR_Test.getVal2(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a CVTSS2SI operator
*
* @param inst the instruction to assemble
*/
private void doCVTSS2SI(OPT_Instruction inst) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SI_Reg_Reg(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SI_Reg_Abs(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SI_Reg_RegDisp(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SI_Reg_RegOff(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitCVTSS2SI_Reg_RegIdx(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitCVTSS2SI_Reg_RegInd(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryAcc instruction
* and has a NEG operator
*
* @param inst the instruction to assemble
*/
private void doNEG(OPT_Instruction inst) {
if (isByte(inst)) {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_UnaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitNEG_Reg_Byte(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitNEG_Abs_Byte(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegDisp_Byte(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegOff_Byte(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegIdx_Byte(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitNEG_RegInd_Byte(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
emitNEG_Reg_Word(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitNEG_Abs_Word(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegDisp_Word(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegOff_Word(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegIdx_Word(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitNEG_RegInd_Word(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
emitNEG_Reg(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitNEG_Abs(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegDisp(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegOff(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitNEG_RegIdx(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitNEG_RegInd(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a SUB operator
*
* @param inst the instruction to assemble
*/
private void doSUB(OPT_Instruction inst) {
if (isReg(MIR_BinaryAcc.getResult(inst))) {
if (isByte(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_Reg_Imm_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_Reg_Reg_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_Reg_Abs_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_Reg_RegDisp_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_Reg_RegOff_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_Reg_RegIdx_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_Reg_RegInd_Byte(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_Imm_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_Reg_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_Abs_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_RegDisp_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_RegOff_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_RegIdx_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_Reg_RegInd_Word(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_Imm(
getReg(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isReg(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isAbs(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_Abs(
getReg(MIR_BinaryAcc.getResult(inst)),
getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_RegDisp(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_RegOff(
getReg(MIR_BinaryAcc.getResult(inst)),
getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
emitSUB_Reg_RegIdx(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_Reg_RegInd(
getReg(MIR_BinaryAcc.getResult(inst)),
getBase(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
} else {
if (isImm(MIR_BinaryAcc.getValue(inst))) {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSUB_Abs_Imm_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegDisp_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegOff_Imm_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegIdx_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUB_RegInd_Imm_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSUB_Abs_Imm_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegDisp_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegOff_Imm_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegIdx_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUB_RegInd_Imm_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
emitSUB_Abs_Imm(
getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegDisp_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegOff_Imm(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
emitSUB_RegIdx_Imm(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitSUB_RegInd_Imm(
getBase(MIR_BinaryAcc.getResult(inst)),
getImm(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
} else {
if (isByte(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_Abs_Reg_Byte(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_RegDisp_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_RegOff_Reg_Byte(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_RegIdx_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !(getReg(MIR_BinaryAcc.getValue(inst)) < 4)) VM._assert(false, inst.toString());
emitSUB_RegInd_Reg_Byte(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isWord(inst)) {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_Abs_Reg_Word(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_RegDisp_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_RegOff_Reg_Word(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_RegIdx_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_RegInd_Reg_Word(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
} else {
if (isAbs(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_Abs_Reg(
getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_RegDisp_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_RegOff_Reg(
getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_RegIdx_Reg(
getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitSUB_RegInd_Reg(
getBase(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_UnaryAcc instruction
* and has a NOT operator
*
* @param inst the instruction to assemble
*/
private void doNOT(OPT_Instruction inst) {
if (isByte(inst)) {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
if (VM.VerifyAssertions && !(getReg(MIR_UnaryAcc.getResult(inst)) < 4)) VM._assert(false, inst.toString());
emitNOT_Reg_Byte(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitNOT_Abs_Byte(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegDisp_Byte(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegOff_Byte(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegIdx_Byte(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitNOT_RegInd_Byte(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
} else {
if (isWord(inst)) {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
emitNOT_Reg_Word(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitNOT_Abs_Word(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegDisp_Word(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegOff_Word(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegIdx_Word(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitNOT_RegInd_Word(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_UnaryAcc.getResult(inst))) {
emitNOT_Reg(
getReg(MIR_UnaryAcc.getResult(inst)));
} else {
if (isAbs(MIR_UnaryAcc.getResult(inst))) {
emitNOT_Abs(
getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegDisp(
getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegOff(
getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
emitNOT_RegIdx(
getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
} else {
if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(false, inst.toString());
emitNOT_RegInd(
getBase(MIR_UnaryAcc.getResult(inst)));
}
}
}
}
}
}
}
}
/**
* Emit the given instruction, assuming that
* it is a MIR_BinaryAcc instruction
* and has a FMULP operator
*
* @param inst the instruction to assemble
*/
private void doFMULP(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isReg(MIR_BinaryAcc.getValue(inst))) VM._assert(false, inst.toString());
emitFMULP_Reg_Reg(
getReg(MIR_BinaryAcc.getResult(inst)),
getReg(MIR_BinaryAcc.getValue(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Nullary instruction
* and has a FLDZ operator
*
* @param inst the instruction to assemble
*/
private void doFLDZ(OPT_Instruction inst) {
if (VM.VerifyAssertions && !isReg(MIR_Nullary.getResult(inst))) VM._assert(false, inst.toString());
emitFLDZ_Reg(
getReg(MIR_Nullary.getResult(inst)));
}
/**
* Emit the given instruction, assuming that
* it is a MIR_Unary instruction
* and has a MOVSX operator
*
* @param inst the instruction to assemble
*/
private void doMOVSX(OPT_Instruction inst) {
if (isByte(inst)) {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVSX_Reg_Reg_Byte(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVSX_Reg_Abs_Byte(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVSX_Reg_RegDisp_Byte(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVSX_Reg_RegOff_Byte(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
emitMOVSX_Reg_RegIdx_Byte(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
emitMOVSX_Reg_RegInd_Byte(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
} else {
if (isReg(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVSX_Reg_Reg_Word(
getReg(MIR_Unary.getResult(inst)),
getReg(MIR_Unary.getVal(inst)));
} else {
if (isAbs(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVSX_Reg_Abs_Word(
getReg(MIR_Unary.getResult(inst)),
getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegDisp(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVSX_Reg_RegDisp_Word(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegOff(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVSX_Reg_RegOff_Word(
getReg(MIR_Unary.getResult(inst)),
getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (isRegIdx(MIR_Unary.getVal(inst))) {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVSX_Reg_RegIdx_Word(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
} else {
if (VM.VerifyAssertions && !isReg(MIR_Unary.getResult(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(false, inst.toString());
if (VM.VerifyAssertions && !isWord(inst)) VM._assert(false, inst.toString());
emitMOVSX_Reg_RegInd_Word(
getReg(MIR_Unary.getResult(inst)),
getBase(MIR_Unary.getVal(inst)));
}
}
}
}
}
}
}
/**
* The number of instructions emitted so far
*/
private int instructionCount = 0;
/**
* Assemble the given instruction
*
* @param inst the instruction to assemble
*/
public void doInst(OPT_Instruction inst) {
resolveForwardReferences(++instructionCount);
switch (inst.getOpcode()) {
case IA32_DIVSS_opcode:
doDIVSS(inst);
break;
case IA32_CMPXCHG8B_opcode:
doCMPXCHG8B(inst);
break;
case IA32_SUBSD_opcode:
doSUBSD(inst);
break;
case IA32_FDIVP_opcode:
doFDIVP(inst);
break;
case IA32_CMPEQSS_opcode:
doCMPEQSS(inst);
break;
case IA32_FCOMIP_opcode:
doFCOMIP(inst);
break;
case IA32_UCOMISD_opcode:
doUCOMISD(inst);
break;
case IA32_CVTTSD2SI_opcode:
doCVTTSD2SI(inst);
break;
case IA32_FCOMI_opcode:
doFCOMI(inst);
break;
case IA32_SHR_opcode:
doSHR(inst);
break;
case IA32_CMPNESD_opcode:
doCMPNESD(inst);
break;
case IA32_AND_opcode:
doAND(inst);
break;
case IA32_BTC_opcode:
doBTC(inst);
break;
case IA32_FLDL2T_opcode:
doFLDL2T(inst);
break;
case IA32_FISTP_opcode:
doFISTP(inst);
break;
case IA32_FDIV_opcode:
doFDIV(inst);
break;
case IA32_ROR_opcode:
doROR(inst);
break;
case IA32_CVTSS2SD_opcode:
doCVTSS2SD(inst);
break;
case IA32_FLDLN2_opcode:
doFLDLN2(inst);
break;
case IA32_FIADD_opcode:
doFIADD(inst);
break;
case IA32_FLD_opcode:
doFLD(inst);
break;
case IA32_FISUBR_opcode:
doFISUBR(inst);
break;
case IA32_MOVD_opcode:
doMOVD(inst);
break;
case IA32_FLDPI_opcode:
doFLDPI(inst);
break;
case IA32_FDIVR_opcode:
doFDIVR(inst);
break;
case IA32_CVTSI2SS_opcode:
doCVTSI2SS(inst);
break;
case IA32_POP_opcode:
doPOP(inst);
break;
case IA32_FILD_opcode:
doFILD(inst);
break;
case IA32_MOV_opcode:
doMOV(inst);
break;
case IA32_MOVZX__B_opcode:
case IA32_MOVZX__W_opcode:
doMOVZX(inst);
break;
case IA32_FLDL2E_opcode:
doFLDL2E(inst);
break;
case IA32_CMPNLTSS_opcode:
doCMPNLTSS(inst);
break;
case IA32_MOVQ_opcode:
doMOVQ(inst);
break;
case IA32_FSUBRP_opcode:
doFSUBRP(inst);
break;
case IA32_CDQ_opcode:
doCDQ(inst);
break;
case IA32_FPREM_opcode:
doFPREM(inst);
break;
case IA32_DIVSD_opcode:
doDIVSD(inst);
break;
case IA32_PAUSE_opcode:
doPAUSE(inst);
break;
case IA32_MOVSS_opcode:
doMOVSS(inst);
break;
case IA32_RDTSC_opcode:
doRDTSC(inst);
break;
case IA32_FINIT_opcode:
doFINIT(inst);
break;
case IA32_MULSD_opcode:
doMULSD(inst);
break;
case IA32_CVTTSS2SI_opcode:
doCVTTSS2SI(inst);
break;
case IA32_FNSAVE_opcode:
doFNSAVE(inst);
break;
case IA32_MULSS_opcode:
doMULSS(inst);
break;
case IA32_CMOV_opcode:
doCMOV(inst);
break;
case IA32_MUL_opcode:
doMUL(inst);
break;
case IA32_XORPD_opcode:
doXORPD(inst);
break;
case IA32_FUCOMI_opcode:
doFUCOMI(inst);
break;
case IA32_FIST_opcode:
doFIST(inst);
break;
case IA32_FISUB_opcode:
doFISUB(inst);
break;
case IA32_XOR_opcode:
doXOR(inst);
break;
case IA32_SHLD_opcode:
doSHLD(inst);
break;
case IA32_DIV_opcode:
doDIV(inst);
break;
case IA32_SET__B_opcode:
doSET(inst);
break;
case IA32_UCOMISS_opcode:
doUCOMISS(inst);
break;
case IA32_RCR_opcode:
doRCR(inst);
break;
case IA32_RET_opcode:
doRET(inst);
break;
case IA32_ADD_opcode:
doADD(inst);
break;
case IA32_FCHS_opcode:
doFCHS(inst);
break;
case IA32_SAR_opcode:
doSAR(inst);
break;
case IA32_CMPLESS_opcode:
doCMPLESS(inst);
break;
case IA32_CMPORDSD_opcode:
doCMPORDSD(inst);
break;
case IA32_FCMOV_opcode:
doFCMOV(inst);
break;
case IA32_FSUB_opcode:
doFSUB(inst);
break;
case IA32_SHL_opcode:
doSHL(inst);
break;
case IA32_FSTP_opcode:
doFSTP(inst);
break;
case IA32_ROL_opcode:
doROL(inst);
break;
case IA32_INC_opcode:
doINC(inst);
break;
case IA32_FIDIVR_opcode:
doFIDIVR(inst);
break;
case IA32_MOVSD_opcode:
doMOVSD(inst);
break;
case IA32_CVTSD2SI_opcode:
doCVTSD2SI(inst);
break;
case IA32_ADC_opcode:
doADC(inst);
break;
case IA32_XORPS_opcode:
doXORPS(inst);
break;
case IA32_BTS_opcode:
doBTS(inst);
break;
case IA32_PUSH_opcode:
doPUSH(inst);
break;
case IA32_IDIV_opcode:
doIDIV(inst);
break;
case IA32_CMPNLESS_opcode:
doCMPNLESS(inst);
break;
case IA32_CMPEQSD_opcode:
doCMPEQSD(inst);
break;
case IA32_LEA_opcode:
doLEA(inst);
break;
case IA32_CMPXCHG_opcode:
doCMPXCHG(inst);
break;
case IA32_OR_opcode:
doOR(inst);
break;
case IA32_CMP_opcode:
doCMP(inst);
break;
case IA32_IMUL2_opcode:
doIMUL2(inst);
break;
case IA32_CMPLTSS_opcode:
doCMPLTSS(inst);
break;
case IA32_FDIVRP_opcode:
doFDIVRP(inst);
break;
case IA32_CMPUNORDSD_opcode:
doCMPUNORDSD(inst);
break;
case IA32_ADDSD_opcode:
doADDSD(inst);
break;
case IA32_SHRD_opcode:
doSHRD(inst);
break;
case IA32_FRSTOR_opcode:
doFRSTOR(inst);
break;
case IA32_BSWAP_opcode:
doBSWAP(inst);
break;
case IA32_INT_opcode:
doINT(inst);
break;
case IA32_CMPNLTSD_opcode:
doCMPNLTSD(inst);
break;
case IA32_CMPUNORDSS_opcode:
doCMPUNORDSS(inst);
break;
case IA32_CVTSI2SD_opcode:
doCVTSI2SD(inst);
break;
case IA32_FSUBR_opcode:
doFSUBR(inst);
break;
case IA32_SBB_opcode:
doSBB(inst);
break;
case IA32_CMPNESS_opcode:
doCMPNESS(inst);
break;
case IA32_FLDLG2_opcode:
doFLDLG2(inst);
break;
case IA32_FNSTCW_opcode:
doFNSTCW(inst);
break;
case IA32_PREFETCHNTA_opcode:
doPREFETCHNTA(inst);
break;
case IA32_FIDIV_opcode:
doFIDIV(inst);
break;
case IA32_CMPLTSD_opcode:
doCMPLTSD(inst);
break;
case IA32_SAL_opcode:
doSAL(inst);
break;
case IA32_FUCOMIP_opcode:
doFUCOMIP(inst);
break;
case IA32_BT_opcode:
doBT(inst);
break;
case IA32_FADDP_opcode:
doFADDP(inst);
break;
case IA32_FLD1_opcode:
doFLD1(inst);
break;
case IA32_FST_opcode:
doFST(inst);
break;
case IA32_FNINIT_opcode:
doFNINIT(inst);
break;
case IA32_CMPORDSS_opcode:
doCMPORDSS(inst);
break;
case IA32_OFFSET_opcode:
doOFFSET(inst);
break;
case IA32_FXCH_opcode:
doFXCH(inst);
break;
case IA32_IMUL1_opcode:
doIMUL1(inst);
break;
case IA32_FSUBP_opcode:
doFSUBP(inst);
break;
case IA32_ADDSS_opcode:
doADDSS(inst);
break;
case IA32_BTR_opcode:
doBTR(inst);
break;
case IA32_SUBSS_opcode:
doSUBSS(inst);
break;
case IA32_FFREE_opcode:
doFFREE(inst);
break;
case IA32_RCL_opcode:
doRCL(inst);
break;
case IA32_CMPLESD_opcode:
doCMPLESD(inst);
break;
case IA32_FLDCW_opcode:
doFLDCW(inst);
break;
case IA32_FIMUL_opcode:
doFIMUL(inst);
break;
case IA32_DEC_opcode:
doDEC(inst);
break;
case IA32_FMUL_opcode:
doFMUL(inst);
break;
case IA32_FADD_opcode:
doFADD(inst);
break;
case IA32_CALL_opcode:
doCALL(inst);
break;
case IA32_FSTCW_opcode:
doFSTCW(inst);
break;
case IA32_CVTSD2SS_opcode:
doCVTSD2SS(inst);
break;
case IA32_CMPNLESD_opcode:
doCMPNLESD(inst);
break;
case IA32_TEST_opcode:
doTEST(inst);
break;
case IA32_CVTSS2SI_opcode:
doCVTSS2SI(inst);
break;
case IA32_NEG_opcode:
doNEG(inst);
break;
case IA32_SUB_opcode:
doSUB(inst);
break;
case IA32_NOT_opcode:
doNOT(inst);
break;
case IA32_FMULP_opcode:
doFMULP(inst);
break;
case IA32_FLDZ_opcode:
doFLDZ(inst);
break;
case IA32_MOVSX__B_opcode:
case IA32_MOVSX__W_opcode:
doMOVSX(inst);
break;
case IA32_JCC_opcode:
doJCC(inst);
break;
case IA32_JMP_opcode:
doJMP(inst);
break;
case IA32_LOCK_opcode:
emitLockNextInstruction();
break;
case IG_PATCH_POINT_opcode:
emitPatchPoint();
break;
case IA32_FEXAM_opcode:
case IA32_TRAPIF_opcode:
case IA32_FCLEAR_opcode:
case IA32_LOCK_CMPXCHG_opcode:
case IA32_JCC2_opcode:
case IA32_FMOV_opcode:
case IA32_FMOV_ENDING_LIVE_RANGE_opcode:
case IA32_LOCK_CMPXCHG8B_opcode:
case IA32_SYSCALL_opcode:
throw new OPT_OptimizingCompilerException(inst + " has unimplemented IA32 opcode (check excludedOpcodes)");
}
inst.setmcOffset( mi );
}
}